1. Field of the Invention
This invention relates to multivalued mask read-only memories that are designed to store information of multiple bits in a single memory cell.
This application is based on Patent Application No. Hei 11-30680 and Patent Application No. Hei 11-96765 both filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, technology of multivalued cells each storing information of multiple bits is known to actualize large capacities for read-only memories (or ROMs). Japanese Patent Application, First Publication No. Hei 8-297982 discloses an example of a multivalued mask ROM, in which codes are written to a ROM in manufacture by changing thresholds (Vt) of cell transistors. FIG. 9 is a circuit diagram showing a part of a cell array used for the aforementioned multivalued mask ROM. Herein, thresholds Vt0, Vt1, Vt2, Vt3 are respectively set to transistors M00, M10, M01, M11, wherein those thresholds differ from each other in accordance with a relationship of Vt0&lt;Vt1&lt;Vt2&lt;Vt3. For example, a word line WL0 is selected and is changed in electric potential by three steps as shown FIG. 10 from zero level to a prescribed level. Thus, it is possible to read out 2-bit information from the transistor M00 or M01.
In order to change ROM codes of the multivalued mask ROM in manufacture, the thresholds Vt are changed by changing channel ion implantation to the cell transistors.
However, the aforementioned technique suffers from problems, as follows:
A first problem is caused by formation of ROM codes, which are formed by the channel ion implantation before formation of gates. At revision of the ROM codes, it is necessary to change masks in lower layers of integrated circuits. Such changes variously influence post-processes in manufacture of the integrated circuits, so it takes a great number of days in designing the masks and in manufacturing the integrated circuits. For this reason, it takes a longer turnaround time (or TAT) for revision.
A second problem is that the revision of the ROM codes needs a great number of modified masks. In case of a four-valued (or 2-bit) mask ROM, for example, it is necessary to modify at least two masks.
In a method in which ROM codes are written in response to magnitude of the thresholds Vt, it is necessary to change impurity density with respect to each of the cell transistors. In the case of the four-valued mask ROM, it is necessary to perform ion implantation two times, that is, it is necessary to perform ion implantation corresponding to Vt1 and ion implantation corresponding to Vt2 respectively. Herein, an amount of the ion implantation corresponding to Vt2 is greater than an amount of the ion implantation corresponding to Vt1.
Specifically, first ion implantation corresponding to Vt1 is performed with respect to the cell transistors corresponding to Vt1, Vt3 by using a first mask, and second ion implantation corresponding to Vt2 is performed with respect to the cell transistors corresponding to Vt2, Vt3 by using a second mask.
As described above, the ion implantation is performed two times on the cell transistor corresponding to Vt3, which has a largest amount of ion implantation and a highest impurity density. In addition, ion implantation is not performed on the cell transistor corresponding to Vt0, which has a lowest impurity density. Thus, using two masks, it is possible to establish a relationship in impurity density in which Vt0&lt;Vt1&lt;Vt2&lt;Vt3.
A third problem is a limitation of integration of the integrated circuits due to an alignment accuracy of ion implantation and spread diffusion of impurities. This is because heat treatment corresponding to the post-process of the ion implantation broadens impurities-diffused regions so that it is impossible to reduce gate pitches so much.
In order to form cell transistors, having different thresholds, to adjoin each other in a same active region, the known CMOS process (where "CMOS" is an abbreviation for "Complementary Metal-Oxide Semiconductor") in mass production provides a gate length of 0.25 .mu.m with a minimum gate pitch of 0.5 .mu.m or so. Such a minimum gate pitch is determined by the alignment accuracy of the ion implantation and the spread diffusion of impurities. For this reason, it will not be reduced so much even if fine manufacture of the CMOS process is developed.
A fourth problem is complication in potential control of the word line(s) to read out codes stored in cells. That is, the aforementioned method that changes thresholds uses a number of different thresholds, which is identical to a number of states being stored in one cell. To discriminate them, it is necessary to control the word line to be at each of different potential levels, a number of which is smaller than the number of states being stored in one cell by "1". In the case of the four-valued mask ROM, it is necessary to control the word line to be at each of "three" potential levels as shown in FIG. 10.